device.h

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#ifndef __xwcd_peripheral_spi_flash_w25qxx_device_h__
#define __xwcd_peripheral_spi_flash_w25qxx_device_h__
 
#include <xwos/standard.h>
#include <xwcd/ds/spi/peripheral.h>
 
#define XWDS_W25QXX_CMD_MAX_PAYLOAD     256U
 
enum xwds_w25qxx_cmd_em {
        XWDS_W25QXX_CMD_WRITE_DISABLE,
        XWDS_W25QXX_CMD_WRITE_ENABLE,
 
        XWDS_W25QXX_CMD_READ_STATUS_REG_1,
        XWDS_W25QXX_CMD_READ_STATUS_REG_2,
        XWDS_W25QXX_CMD_READ_STATUS_REG_3,
        XWDS_W25QXX_CMD_WRITE_STATUS_REG_1,
        XWDS_W25QXX_CMD_WRITE_STATUS_REG_2,
        XWDS_W25QXX_CMD_WRITE_STATUS_REG_3,
 
        XWDS_W25QXX_CMD_READ_DATA,
        XWDS_W25QXX_CMD_FAST_READ_DATA,
        XWDS_W25QXX_CMD_SET_READ_PARAMETERS,
 
        XWDS_W25QXX_CMD_PAGE_PROGRAM,
 
        XWDS_W25QXX_CMD_32KBLOCK_ERASE,
        XWDS_W25QXX_CMD_64KBLOCK_ERASE,
        XWDS_W25QXX_CMD_SECTOR_ERASE,
        XWDS_W25QXX_CMD_CHIP_ERASE,
 
        XWDS_W25QXX_CMD_POWER_DOWN,
        XWDS_W25QXX_CMD_RELEASE_POWER_DOWN,
 
        XWDS_W25QXX_CMD_UNIQUE_ID,
        XWDS_W25QXX_CMD_MANUFACTURER_DEVICE_ID,
        XWDS_W25QXX_CMD_JEDEC_DEVICE_ID,
 
        XWDS_W25QXX_CMD_ENTER_4BYTE_ADDR_MODE,
        XWDS_W25QXX_CMD_EXIT_4BYTE_ADDR_MODE,
 
        XWDS_W25QXX_CMD_ENTER_QPI_MODE,
        XWDS_W25QXX_CMD_EXIT_QPI_MODE,
 
        XWDS_W25QXX_CMD_ENABLE_RESET,
        XWDS_W25QXX_CMD_RESET,
 
        XWDS_W25QXX_CMD_NUM,
};
 
enum w25q_mid_em {
        XWDS_W25Q80_MID = 0xEF13,
        XWDS_W25Q16_MID = 0xEF14,
        XWDS_W25Q32_MID = 0xEF15,
        XWDS_W25Q64_MID = 0xEF16,
        XWDS_W25Q128_MID = 0xEF17,
        XWDS_W25Q256_MID = 0xEF18,
};
 
enum xwds_w25qxx_sr_idx_em {
        XWDS_W25QXX_SR_1,
        XWDS_W25QXX_SR_2,
        XWDS_W25QXX_SR_3,
        XWDS_W25QXX_SR_NUM,
};
 
enum xwds_w25qxx_sr1_bit_em {
        XWDS_W25QXX_SR1_BUSY = 0x1U,
        XWDS_W25QXX_SR1_WEL = 0x2U,
        XWDS_W25QXX_SR1_BP0 = 0x4U,
        XWDS_W25QXX_SR1_BP1 = 0x8U,
        XWDS_W25QXX_SR1_BP2 = 0x10U,
        XWDS_W25QXX_SR1_TB = 0x20U,
        XWDS_W25QXX_SR1_SEC = 0x40U,
        XWDS_W25QXX_SR1_SRP = 0x80U,
};
enum xwds_w25qxx_sr2_bit_em {
        XWDS_W25QXX_SR2_SRL = 0x1U,
        XWDS_W25QXX_SR2_QE = 0x2U,
        XWDS_W25QXX_SR2_R2 = 0x4U,
        XWDS_W25QXX_SR2_LB1 = 0x8U,
        XWDS_W25QXX_SR2_LB2 = 0x10U,
        XWDS_W25QXX_SR2_LB3 = 0x20U,
        XWDS_W25QXX_SR2_CMP = 0x40U,
        XWDS_W25QXX_SR2_SUS = 0x80U,
};
 
enum xwds_w25qxx_sr3_bit_em {
        XWDS_W25QXX_SR3_R0 = 0x1U,
        XWDS_W25QXX_SR3_R1 = 0x2U,
        XWDS_W25QXX_SR3_WPS = 0x4U,
        XWDS_W25QXX_SR3_R3 = 0x8U,
        XWDS_W25QXX_SR3_R4 = 0x10U,
        XWDS_W25QXX_SR3_DRV0 = 0x20U,
        XWDS_W25QXX_SR3_DRV1 = 0x40U,
        XWDS_W25QXX_SR3_HR = 0x80U,
};
 
struct xwds_w25qxx_cmd {
        xwu8_t existing; 
        xwu8_t instruction; 
        xwu8_t address_size; 
        xwu32_t address; 
        xwu32_t dummy_cycles; 
};
 
struct xwds_w25qxx_parameter {
        xwu32_t size;
        xwu64_t uid;
        xwu16_t mid;
        xwu32_t jid;
};
 
struct xwds_w25qxx {
        struct xwds_spip spip; 
        /* attributes */
        struct xwds_w25qxx_parameter parameter; 
        const struct xwds_w25qxx_cmd * cmdtbl; 
        /* private */
        xwu8_t txq[XWDS_W25QXX_CMD_MAX_PAYLOAD + 16]; 
        xwu8_t rxq[XWDS_W25QXX_CMD_MAX_PAYLOAD + 16]; 
};
 
void xwds_w25qxx_construct(struct xwds_w25qxx * w25qxx);
void xwds_w25qxx_destruct(struct xwds_w25qxx * w25qxx);
 
static __xwds_inline
xwer_t xwds_w25qxx_grab(struct xwds_w25qxx * w25qxx)
{
        return xwds_spip_grab(&w25qxx->spip);
}
 
static __xwds_inline
xwer_t xwds_w25qxx_put(struct xwds_w25qxx * w25qxx)
{
        return xwds_spip_put(&w25qxx->spip);
}
 
#endif /* xwcd/peripheral/spi/flash/w25qxx/device.h */